Thanks very much for all the info wich you provided to allow us hobbiests build a decent drive.
I have a machine running with CPLD drive's from your tutorial and PCB design using your recommendations on PCB layout, it's working fine.
Will try to see what difference the change on the DUMP signal makes.
Writing on the wall was forbidden by my ex-wife and I do forbid it to my grandchild also...
Edit:
I understand the synchronisation function between the step and PWM and I saw those notches also but seem to remember that there was a problem with the timebase counter, as far as I remember: The blanking period period doesn't start at the zero count. This didn't create problems with the original code but did when the code was modified for additional functions.
Have to check my notes but I think these notches were gone when I modified it.