Regarding encoder input to kflop

[amitkumar171]

Dear all


Presently we are using KFLOP board and KMOTION. And we need to find the simple Encoders. For Finding the Encoders we need to know:*


1. what are the Communication Protocols supports KFLOP board and KMOTION for interfacing the Encoders?

2. How many Encoders we can interface which supports KFLOP & KMOTION?

3. Which type of Encoder interfacing you will suggest for the KFLOP?

*

4.**Can we use EnDat 2.2 – Bidirectional Interface Type and TTL interface Type?


Regards



Sent from my Redmi Note 5 Pro using Tapatalk

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[TomKerekes]

Hi Amit,

what are the Communication Protocols supports KFLOP board and KMOTION for interfacing the Encoders?

KFLOP only directly supports digital incremental encoders. See:
http://dynomotion.com/faq.html#Encoders

How many Encoders we can interface which supports KFLOP & KMOTION?

KFLOP has 8 encoder inputs. There are some pinout limitations based on your configuration. The Encoder input pins normally on JP7 and JP5 can be multiplexed over to KFLOP JP4 and JP6. See the MuxEncoders.c example.

Which type of Encoder interfacing you will suggest for the KFLOP?

Differential digital incremental quadrature encoders

Can we use EnDat 2.2 – Bidirectional Interface Type and TTL interface Type?

No. Except sometimes they may include incremental quadrature signals.

Regards

[amitkumar171]

Hi Tom,

Thanks for the information.

As i was planning to use the following series of encoder from heidenhain.

LC415/ LC485/ LF485/ LS487

https://www.heidenhain.com/en_US/pro...lc-400-series/
https://www.heidenhain.com/en_US/pro...-tools/lf-485/
https://www.heidenhain.com/en_US/pro...ls-400-series/

Please help me out with

1. How to use the above encoders with the KLFOP/KANALOG ?

2. Are these encoders compatible with KFLOP/KANALOG Board ?

Waiting for your kind reply.

[TomKerekes]

Hi Amit,

The encoders with the Incremental signals TTL would be compatible with KFLOP/Kanalog.

From the Heidenhain Manuual:



Connect:

Heidenhain Ua1 to Kanalog A+
Heidenhain Ua2 to Kanalog B+
Heidenhain /Ua1 to Kanalog A-
Heidenhain /Ua2 to Kanalog B-

if the reference mark (Ua0 /Ua0) is required it may be connected to any spare A or B input

KFLOP/Kanalog inputs have a max count rate of 1000000 quadrature counts per second. So for example if the resolution is 1um the max velocity would be 1 m/sec.

Regards

[amitkumar171]

Hi Tom,

Thanks for your reply.

I will connect that encoder to Kanalog and will try to run.

And also let you know if any problem occurs.

[amitkumar171]

Ques - Can we use EnDat 2.2 – Bidirectional Interface Type and TTL interface Type?

Ans - No. Except sometimes they may include incremental quadrature signals.

Hi Tom,

As you told "endat" communication not possible for encoders. But, I saw in KANALOG connector specs, in that mentioned Pin no. 15 of JP14 is CLK. So why this CLK pin and What is the frequency in this Pin?

Waiting for your kind reply

[TomKerekes]

Hi Amit,

That is a special clock used in a special manner involved with communicating data from KFLOP to Kanalog. It wouldn't be of any use for interfacing EnDat 2.2 encoders.

Regards

[amitkumar171]

Hi Tom,


Arrow mark shows, CLK is input to the KFLOP. Then How kanalog board providing CLK to KFLOP? Could you tell more.


If we write the the code, Can we generate Clock from any other unused IO's (IO from JP4 or 5 or 6 or 7)? If yes, How much maximum frequency range i can generate?

Waiting for your kind reply.





Sent from my Redmi Note 5 Pro using Tapatalk

[TomKerekes]

Hi Amit,

Arrow mark shows, CLK is input to the KFLOP. Then How kanalog board providing CLK to KFLOP? Could you tell more.

No the Kanalog interface is complex and we don't have it documented and it is not likely to be of any use to you.

If we write the the code, Can we generate Clock from any other unused IO's (IO from JP4 or 5 or 6 or 7)? If yes, How much maximum frequency range i can generate?

Below is a program that generates a clock on IO16 with software and reads a bit each clock.

It prints :Time per clock = 2.07 us, frequency = 483 KHz

#include "KMotionDef.h"

#define CLK 16
#define DATA 17

void main()
{
    double T0, T1;
    int i = 0, k;

    SetBitDirection(CLK, 1);
    SetBitDirection(DATA, 1);
    T0 = Time_sec();
    for (k = 0; k < 8; k++)
    {
        SetBit(CLK);            //Toggle Clock
        ClearBit(CLK);
        i = (i << 1) | ReadBit(DATA);    // Read one bit
    }
    T1 = Time_sec();
    printf("Time per clock = %.2f us, frequency = %.0f KHz\n", (T1 - T0) * 1e6 / 8.0,
           1e-3 / (T1 - T0) * 8.0);
}

Here is a scope of IO16. Note some clock irregularity due to cache and then 641KHz

[amitkumar171]

Hi Amit,

No the Kanalog interface is complex and we don't have it documented and it is not likely to be of any use to you.

Below is a program that generates a clock on IO16 with software and reads a bit each clock.

It prints :Time per clock = 2.07 us, frequency = 483 KHz

#include "KMotionDef.h"

#define CLK 16
#define DATA 17

void main()
{
    double T0, T1;
    int i = 0, k;

    SetBitDirection(CLK, 1);
    SetBitDirection(DATA, 1);
    T0 = Time_sec();
    for (k = 0; k < 8; k++)
    {
        SetBit(CLK);            //Toggle Clock
        ClearBit(CLK);
        i = (i << 1) | ReadBit(DATA);    // Read one bit
    }
    T1 = Time_sec();
    printf("Time per clock = %.2f us, frequency = %.0f KHz\n", (T1 - T0) * 1e6 / 8.0,
           1e-3 / (T1 - T0) * 8.0);
}

Here is a scope of IO16. Note some clock irregularity due to cache and then 641KHz

Dear Tom,


You have mentioned the frequency 483kHz-641kHz. Why can't we generate more frequency like 1MHz-10MHz?

What is the input clock frequency for the FPGA?


Regards,



Sent from my Redmi Note 5 Pro using Tapatalk

[TomKerekes]

Hi Amit,

You have mentioned the frequency 483kHz-641kHz. Why can't we generate more frequency like 1MHz-10MHz?

Because that is the time it takes the code to execute.

What is the input clock frequency for the FPGA?

The FPGA basically operates at 16.67MHz but has access to much higher clock rates. I'm sure the FPGA could be re-programmed to support EnDat 2.2 encoder compatibility. But this would involve developing VHDL code to support it as well as new KFLOP DSP firmware to support reading the absolute values and so forth. This would result in a custom specialized version. Also changes to the PC GUI and documentation. We don't release the FPGA configuration or have documentation to allow User to modify it. If you really require interfacing to these encoders we would consider developing the interface for you for an NRE charge of $10K.

[amitkumar171]

Hi Tom,


Thanks for the information.

I had some more doubts. They are as follows :



1. In the FPGA datasheet it is mentioned that the operating frequency range is 5-300MHZ and 5MHz is the minimum. But like you said currently KFLOP- FPGA is working at <600KHz.
I am sorry but I am a little confused here as to how the FPGA is working at a frequency less than the specified range.


2. Is the FPGA being driven by an external clock? If yes, What is the input frequency presently?


3. Also is the present firmware in C language? If yes, then why do we need to write a new VHDL code ? Why can't it be in C language only?

[TomKerekes]

Hi Amit,

You might study what FPGA's are, how they are used, how they are programmed, etc...

In the FPGA datasheet it is mentioned that the operating frequency range is 5-300MHZ and 5MHz is the minimum. But like you said currently KFLOP- FPGA is working at <600KHz.
I am sorry but I am a little confused here as to how the FPGA is working at a frequency less than the specified range.

The FPGA is not operating at <600KHz, rather the DSP sending commands to the FPGA at <600KHz. For example you might write a C Program to blink an LED at 1Hz. But C Programs take time to execute which limits how fast they can do things.

Also the FPGA can perform logic all the way down to 0Hz. Only certain clock inputs, phase lock loops and such have limited frequency ranges.

Is the FPGA being driven by an external clock? If yes, What is the input frequency presently?

The FPGA is driven by an external 25MHz clock and converted to 16.67MHz internally.

Also is the present firmware in C language? If yes, then why do we need to write a new VHDL code ? Why can't it be in C language only?

The DSP is programmed in C. The FPGA consists basically of 100,000 logic gates that can be reconfigured into hardware devices that operate in parallel. Think of it more like a circuit schematic. C Language would not be appropriate. VHDL is a language used to define logic.

HTH