Hi Amit,
Arrow mark shows, CLK is input to the KFLOP. Then How kanalog board providing CLK to KFLOP? Could you tell more.
No the Kanalog interface is complex and we don't have it documented and it is not likely to be of any use to you.
If we write the the code, Can we generate Clock from any other unused IO's (IO from JP4 or 5 or 6 or 7)? If yes, How much maximum frequency range i can generate?
Below is a program that generates a clock on IO16 with software and reads a bit each clock.
It prints :Time per clock = 2.07 us, frequency = 483 KHz
Code:
#include "KMotionDef.h"
#define CLK 16
#define DATA 17
void main()
{
double T0, T1;
int i = 0, k;
SetBitDirection(CLK, 1);
SetBitDirection(DATA, 1);
T0 = Time_sec();
for (k = 0; k < 8; k++)
{
SetBit(CLK); //Toggle Clock
ClearBit(CLK);
i = (i << 1) | ReadBit(DATA); // Read one bit
}
T1 = Time_sec();
printf("Time per clock = %.2f us, frequency = %.0f KHz\n", (T1 - T0) * 1e6 / 8.0,
1e-3 / (T1 - T0) * 8.0);
}
Here is a scope of IO16. Note some clock irregularity due to cache and then 641KHz