Hi Amit,

You might study what FPGA's are, how they are used, how they are programmed, etc...

In the FPGA datasheet it is mentioned that the operating frequency range is 5-300MHZ and 5MHz is the minimum. But like you said currently KFLOP- FPGA is working at <600KHz.
I am sorry but I am a little confused here as to how the FPGA is working at a frequency less than the specified range.
The FPGA is not operating at <600KHz, rather the DSP sending commands to the FPGA at <600KHz. For example you might write a C Program to blink an LED at 1Hz. But C Programs take time to execute which limits how fast they can do things.

Also the FPGA can perform logic all the way down to 0Hz. Only certain clock inputs, phase lock loops and such have limited frequency ranges.

Is the FPGA being driven by an external clock? If yes, What is the input frequency presently?
The FPGA is driven by an external 25MHz clock and converted to 16.67MHz internally.

Also is the present firmware in C language? If yes, then why do we need to write a new VHDL code ? Why can't it be in C language only?
The DSP is programmed in C. The FPGA consists basically of 100,000 logic gates that can be reconfigured into hardware devices that operate in parallel. Think of it more like a circuit schematic. C Language would not be appropriate. VHDL is a language used to define logic.