Hi Jon,
I'm not sure I fully understand your issue, but yes the inputs on JP5 are floating and if not connected to anything will float to any level and may read random states or often follow the state of an adjacent pin. The inputs are CMOS so are very high impedance (meg ohms).
All KFLOP inputs are 3.3V LVTTL FPGA inputs with diode protection clamping to the 3.3V power rail. Some pins (all JP5 pins and some JP7pins) have a series 47 ohm resistor which allows the pin to be driven to 5V without damage. However when this happens the protection diode draws a fair amount of current and bleeds some small current into an adjacent pin in some cases. This doesn't cause any major problems but should be avoided if possible by not driving the pin above 3.8V. Most 5V TTL outputs do not drive above 3.8V.
IO pins on KFLOP JP4 and JP6 are 3.3V only and will cause damage if driven to +5V. But the first 8 of 10 IO on each connector have strong 150ohm termination resistors (pull downs) that may work better for you.
HTH