After a 3 year absence, I finally got around to building a drive based on the information presented by Mariss in the "5 Microstep drive CPLD tutorial" threads. The circuit is essentially the one presented at the end of that document. I added the JTAG programming port and the voltage regulators. The board is double sided, made by toner transfer, with .05" vias and 12 mil traces. The layout is very roughly based on the Geckodrive G251. As it turned out, this is not suitable for my toner transfer board because the unevenness and the lack of through hole plating made it impossible to clamp the fets down. I will try a different fet layout on the next iteration.
The verilog code is the one posted by Pminmo. I made changes to support 10 instead of 5 microsteps. I am currently testing it on a Keling kl23h276-30-8b nema 23, 280 oz-in, 4 amp stepper.
Driving it with 33v and 2 amps, I am able to reach 1800 rpm unloaded, which is the maximum limits of the demo version of Mach 3. I applied a very simple mechanical resonance damper to prevent the motor from stalling.
It is still work in progress. Because I don't have a ground plane, it is difficult to avoid parasitic inductances which resulted in periodic oscillations from the mosfets. I was able to stop them by using gate resistors, but seems to cause severe shoot through. I am experimenting with different solutions. I will probably need to redo the power section.
At least 2 others have photo evidence of their project, but I did not see any writeup on a fully working one yet. I'm surprised that there hasn't been more activity with this design. In my opinion, it is one of, if not the most capable open source stepper drive presented on the web. The project require more development before it's ready, but it's a great leaning tool for learning verilog and mosfet power design.
Here's a shot of the resonance damper that I've been playing with. It's simply a gear from the mini-lathe. I had an assortment to pick from. The one in the photo is about 2" in diameter. The gear fits loosely on the shaft. The key slot is slightly oversized relative to the key. The disc (gear) normally rotates with the shaft. But when resonance occur, the key rattle against the slot. This dissipates the energy and dampens the oscillation.
It worked very well.
Thanks for the pointer to the info.
I'm not quite ready to learn about CPLD programming, but I would like to know more about working with power MOSFETs, and figured that this might be a useful source...
Last edited by ger21; 01-29-2012 at 01:56 PM. Reason: advertising
1. EMI. There's more ringing in the waveform than I would like. It manifest as snow on a weak TV channel.
2. I had to disable the fast decay mode. When enabled, the pwm freq becomes 10khz instead of 20. I think it's caused by shoot through or ringing, causing the winding to need 2 cycles to reach the set point.
Athough the slow decay waveform does not good on the scope, I actually think it works pretty well. But I don't have anything to compare to. Perhaps the vibration damper would not rattle as much if the waveform stayed sinusoidal at higher frequencies.
3. The drive has a very soft hiss at one of the microstep postion. This is minor, but I like to see if I can eliminate it.
I think all the issues are related to the layout of the power section. I think I will try grafting on other layouts to see what works best.
I added gate resistors to each of the upper mosfets. This eliminated the 1Mhz oscillations that produced the intermittent hissing noise.
The big issue remaining is why the PWM frequency falls to 10 Khz when the fast decay mode is enabled. The attached trace shows the waveform across the current sensing resistor. Vertical scale is 1 amp/div. Timebase is 50uS/div.
I suspect that it's due to the lack of slope compensation when the motor is stepping. The PWM duty cycle appears to be alternating between zero and 100%.
I added slope compensation during stepping. That corrected the PWM frequency problem.
The fast decay mode actually seems to vibrate more than the recirculating one. I noticed no improvement in performance. However, I notice a glitch at the 0 and 90 degree sine positions. .
The cause is a mystery at this point.
On a more general level: Is there a real point to learning / using CPLD's these days given the availability of very low cost, very fast microcontrollers? It would seem like most of what you are doing could be accomplished in uC firmware using C or ASM without having to learn an HDL like verilog / VHDL. Or is there some advantage that the CPLD brings that a uC can't possibly provide?
The key is to use the proper tool for the job. Both has strengths and weaknesses.
Technically, you could do everything with a micro, but even a fast mcu is much slower since the code is executed sequentially. Verilog code translate into hardware connections inside the cpld which runs in parallel. A simple example would be the pwm sine wave code. On a mcu without PWM, much of your cpu cycles would be used up. You would need to worry about responding to other events fast enough to avoid jitter. With a cpld, your primary concern is running out of gates to connect. Speed is not an issue when doing motor controllers.
Learning verilog is no harder than learning another assembly language. You only need to learn a small subset in order to do a lot. I'm a pure novice at this point.
The biggest limitation of cplds is that you have very limited resources to work with when compared to a mcu. This make experimentation more difficult. My next project will involve using a DSP to do the same thing. The ones designed for motor control have so much goodies on board. I like to see how well they work.