The 8085 doesn't seem to be doing so well. Both ALE (pin 30) and RESET_OUT (pin 3) have nothing but 100mV of noise on them. On the input side, /RESET_IN looks fine: +4.96 VDC and steady, and CLK_(OUT) is a reasonable looking 4.40 volt square wave at 3.2 MHz, which I'm pretty sure is right for this version: 8085AH was speced at 3 MHz system clock, and the stamp on the crystal confirms this: 6.1440 MHz, where the system clock runs at crystal/2.
Isn't RESET_OUT supposed to just inversely follow /RESET_ IN, with state transitions synced to the system clock? Also, as you pointed out, the manuals seem to think that most instruction cycles require ALE to be asserted when the lower address byte is stable, so ALE should have a fairly regular square wave on it, right?