UP/DOWN COUNTER

[Elijah Turner]

UP/DOWN COUNTER I am a student designing a digital feedback control system as a project and am having difficulty with the logic that compares the number of move pulses from a microcontroller (MC68HC11) with the number of feedback pulses from the encoder. These pulses need to be subtracted to determine if the DC motor is ahead or behind the desired position so that the duty cycle of the PWM can be changed as needed. The problem is that both pulse streams are asychronous and pulses from both streams could arrive at an up/down counter at the same time. QUESTION: What logic circuit could capture both streams and subtract them without occasionally loosing a pulse? Your thoughts will be greatly appreciated. Elijah the Student.

[Eurisko]

Elijah,

My first instinct was to capture the pulses with a flip flop, then work on from there.

Maybe a little more info is needed.

What is the maximum pulse rate?
Will discrete logic chips be used, or will the microcontroller handle most of the work?

If you could expand on a few details of your design, it might just get the ball rolling.

[Lew Hartswick]

Rather than keeping track of pulses on two non sync pulsetrains why not use
a charge balancing scheme. One pulsetrain adds to the charge while the other
subtracts. This way the error is zero when balanced and the polarity and
magnitude represents the sign and magnitude of error.
"Think analog" :-)
...lew...

[kreutz]

It is not so simple, and all depends on the pulse repetition rate (prr) from the encoder and input pulse rate from your micro-controller.

On a micro-controller based solution you will need to decode the encoder's quadrature output and generate an interrupt on every transition (x4 decoder) to read A and B channels, then use an up/down pulse accumulator just to count the pulses, that can be done at low to medium prr (and if the overhead on your micro-controller is not too much).

There are chips which already include the decoder, up/down 16 or 32 bits counter and latch with parallel or SPI interface for higher ppr. Or you can design one on a CPLD.

You don't have to subtract both counts on the same interrupt routine you use to count the pulses in a software solution. Normally the PID routine has an associated low interrupt rate (between 1Khz and 10 Khz) and you can make the subtraction part of that routine (only if your counters don't overflow in the interval between interrupts).

For faster counting (and reducing latency to other interrupts) your encoder interrupt routine just reads the port and places the resulting two bits in a queue, re-enabling interrupts afterward. A tick clock interrupt routine (runs with interrupts re-enabled) will process the values and update the absolute position (comparing the phase between last received two bits and new received bits) and flagging an error if they are out of sequence.

Your control loop routine will read the values of the variables you use for encoder position and input pulse accumulator (treated the same way as the encoder pulses), subtract them (to calculate the error), and do the necessary calculations to generate the duty cycle of the PWM.

[vger]

Elijah,
I remember seeing a single IC somewhere that has inputs for and incrimental encoder, and step / direction. I think it had an up / down counter and a DAC onboard to output an analog voltage that could be used to drive a servo amp. The purpose was to drive a servo motor using step / direction signals from a controller. If I remember rightly, the thing would only error out if the it counted more than 128/127 pulses off center which would lend to an 8 bit UP / Down counter. I'm not sure how they did the logic on the chip. I'll see if I can locate that chip again.

Steve

[kreutz]

Originally Posted by vger Elijah, I remember seeing a single IC somewhere that has inputs for and incrimental encoder, and step / direction. I think it had an up / down counter and a DAC onboard to output an analog voltage that could be used to drive a servo amp. The purpose was to drive a servo motor using step / direction signals from a controller. If I remember rightly, the thing would only error out if the it counted more than 128/127 pulses off center which would lend to an 8 bit UP / Down counter. I'm not sure how they did the logic on the chip. I'll see if I can locate that chip again. Steve

That is a rare finding, I would like to know more about that chip. But for Elijah's project will make a poor learning experience.

A real life design project is not simply a cut and paste exercise. That will make you become what most of the chip vendors want to have as customers, and will create a technology dependent product. You will only learn to read data-sheets and interface them using the application notes. A real learning experience it to solve the problem without using specialized chips (or reducing them to a minimum).

The information on that chip would be a good starting point for the project, if Elijah emulates it on his micro-controller (some additional logic could be required).

Elijah;

About making asynchronous inputs synchronous, is is very easy and explained on most of the CPLD and FPGA getting-started schematic capture literature, you can also create some simple digital filtering to the encoder and step/Dir pulses without too much overhead.

Kreutz.

[Mariss Freimanis]

I can think of two two ways of solving the problem:

1) Have 2 UD counters, counter A gets one source, while counter B gets the other source. Counter A and B outputs go to an adder, the sum being the difference between the two counters.

Example:
CNT_A = 0x00, CNT_B = 0x80. A + B = 0x80
CNT_A = 0xFF, CNT_B = 0x81. A + B = 0x80 (A-1, B+1)
CNT_A = 0x7F, CNT_B = 0x01. A + B = 0x80 (A-128, B+128) etc.

The above requires 2 counters and an adder. It is elegant, simple and is a good solution for a microprocessor. Increment reg B for CW direction, decrement reg A for CW direction, sum reg A and B for the position difference.

2) Counters and adders are "expensive" (use a lot of resources) in a CPLD. The solution is a single UD counter that has anti-collision gating on its UD and CE inputs as shown in the attached gif. Since this is homework, I leave it to you to puzzle-out how the gating works. Hint: Draw timing charts for the circuit. It is a fully synchronous design, it works with any STP pulse-width and DIR must be true only at the falling edge of the STP inputs. The STP pulse input rate must not exceed 1/4 the synchronous CLK frequency (5MHz in our design). We use this circuit in our CPLD servodrive so you know it works.

Mariss

[vger]

Kreutz,

Can't find that thing. Should have saved it in favs. Will keep looking though.
Yeah, buying it would be cheating the learning process. Thought the chip datasheet might have some details on how they did it.

Elijah,
If you want to do this all in disctete IC's, I think your board acreage may be fair sized. I would say first you should decode the encoder pulses to step/dir so they match what is coming from the microcontroller (assuming that is what they are) and use 4 edge triggered F/F's storing the up/down info. Scan the four F/F outputs (dual data selector/multiplexer) at a rate that is many times the maximum PRR from the encoder or microcontroller. Reset the F/F's at the end of each scan. Output of the 2 data selectors go to the up down counter chain count inputs. Use presettable U/D counters so you can preset them mid count on power up. From that point there are options, digital pulse width using magnitude comparitors and a free running counter, or DAC and an analog PWM circuit.

Sounds like a good project.
Steve

[Mariss Freimanis]

Same as above but with an X4 quadrature decoder.

Mariss