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Thread: KKonnect - KFlop

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    Default KKonnect - KFlop

    Tom, good day!
    I connect IO module MPG Siemens (Chiron 25FZ) to KFLOP. The module is connected via my adapter instead KKonnect. You can send the protocol between KKonect and Kflop or is classified information?

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    Default Re: KKonnect - KFlop

    The attached PDF is the Konnect standard Tom provided me with a while ago, and the word document is one with my notes added from when I tried to use an STM32 to communicate instead of a Konnect board, with the aim of implementing a Modbus interface to a remote IO board.
    However, even with an STM32 clocked to 172MHz, I couldn't get it to respond fast enough. It should be a reasonably simple thing to implement in a FPGA for those with the skills to program such things.

    One thing I learnt though, is the Konnect board is such a simple thing when you realise just how simple the logic involved is!

    Attached Thumbnails Attached Thumbnails KKonnect - KFlop-konnect-protocol-pdf   KKonnect - KFlop-timing_pt1-jpg   KKonnect - KFlop-timing_pt2-jpg  
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    Default Re: KKonnect - KFlop

    M_c, many thanks!
    I'll try to implement without the FPGA. Signature bytes are always the same?



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    Default Re: KKonnect - KFlop

    Protocol in the subject, unfortunately, not true.
    Latching addresses and registers on the output registers occurs on the falling edge.
    Does anyone have any information whether at some point there is latching on KFLOP input0-input4?



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    Default Re: KKonnect - KFlop

    Hi Smouk,

    While the CLK is high the Konnect board drives the data Bus with the current Input Data. After some time KFLOP reads the data (which latches the data) then quickly puts the CLK low.

    HTH
    Regards

    TK
    http://dynomotion.com


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    Default Re: KKonnect - KFlop

    I forgot to write. For those who will be repeated this way:
    KKonnect - KFlop-konnect-jpg
    Channel:
    1. CLKIN (pin 15).
    2. STARTIN (pin 16).
    3. DB0 (pin 5).
    4. DB1 (pin 6).

    Arrows:
    Red - capture address on the falling edge STARTIN.
    Brown - capture output on the falling edge CLK (8х2 = 16 output).
    Green - setting the input value of the data lines on the rising edge CLK( 8x4 = 32 input + 8 check bit). The value of the last input fixedly to check - 0xA5.

    Use in the scheme of microcontrollers - not work idea, time delays are too small. If you need an adapter to IO module is necessary to use the FPGA.

    Attached Thumbnails Attached Thumbnails KKonnect - KFlop-konnect-jpg  


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