Originally Posted by H500  Sounds like another chip with a built-in design error. |
Well unlike the Allegro chip with a similar problem, LSI are quite candid about this... the LS7290 is a replacement functionally for the 297 in 1/2 and full step modes only but the internal logic wont provide current feedback for other modes and they suggest using external sense components or reducing supply voltage as appropriate.
Here is the relevant info from the tech note:
Duty Cycles of active-low Outputs, INH1/ & INH2/: The duty cycles of INH1/ and INH2/ outputs are fixed per table 2 of the LS7290 datasheet.
The SENSE1 and SENSE2 inputs are provided for over-current protection only, not for chopping control of the drive outputs.
In any stepping mode other than the full-step and the half-step modes, if the inhibit outputs are truncated due to the SENSE inputs reaching the VREF level, the fixed duty cycle ratios of the INH1/ and the INH2/ will be disrupted leading to motor misstep.
Therefore, in modes other than the full-step and half-step, the SENSE1 and SENSE2 inputs should be tied to ground and the VREF input should be tied to the positive rail. Under these circumstances, if over-current becomes an issue, it can only be resolved by lowering the motor supply voltage.
In the full-step and the half-step modes however, since the fixed duty cycle ratios for the two inhibit outputs are 100%-0% and 70.7%-70.7%, the SENSE inputs can be utilized for chopping the INH1/ and INH2/ outputs, without disrupting the duty cycle ratio. Therefore, in full and half step modes SENSE input chopping can be used for motor current regulation.
When the SENSE inputs are used for output chopping, the INH1/ and the INH2/ outputs are terminated (switched low) when the corresponding SENSE input becomes equal to the VREF. The maximum voltage at VREF= 3V, when chopping is used.
For fixed PWM, the duty cycles in table2 are adjusted within a 32us window based on 8MHz clock. For reference, this will translate to 22.6us on and 9.4us off for a 70.7% duty cycle.