OK, let's start. Please see the attached gif.
The schematic is for a half-step chopper drive scaled for 7A @ 80VDC maximum. The diagram shows the CPLD and the external circuit for winding A. The winding B circuit is identical so there is no point in repeating it. The trimpot adjusts the set current from 0 to 7A.
The constant off-time chopper algorithm is:
1) Apply voltage to the motor coil (LA = 1, RA = 0).
2) Ignore the comparator signal (CMPA) for 5uS to allow transients to die away.
3) Input CMPA goes low when current reaches reference level.
4) When CMPA goes low, compliment LA and RA (LA = 0, RA = 1) for 20uS.
5) Go back to (1).
STP and DIR go to a 3-bit UD counter whose outputs are called QA. These outputs go to phase decoders A and B. The decoders generate the motor winding current direction (input to XOR gate), synchronize the 5uS and 20uS timers to the STP input (via RES) and modulate the winding's current amplitude (via REFA) to generate the necessary half-step waveform.
You can think of a half-step drive as a 2 microstep drive. Here current is either 'set current' or zero. Higher resolution microstepping would have REFA generate other current levels between zero and 'set current'.
If anything so far is unclear or needs better explanation, please ask.
Next up: Designing the clock oscillator and step counter.
Mariss |